集成电路的失效分析

Dynamic random-access memory (DRAM) is one of the basic units used in most of the electronic devices including laptops, smartphones, personal computers etc. The crucial elements of such devices are capacitors and transistors. The FET transistor creates an access (based on gate contact signal) to the capacitor unit which is charged and hence the bit information is stored. The charge on the capacitor drains slowly, therefore, the information needs to be refreshed periodically, reason of which, this memory is called dynamic.

Scanning Electron Microscopy (SEM) inspection is part of routine processes of root-cause failure analysis in semiconductor foundries. There is a wide range of SEM applications for fault isolation tasks that include end-point detection during delayering processes of integrated circuits (ICs) in which electrical nanoprobing is an additional task also enabled by SEM. SEM can also be used to localise and mark bits on the delayered chips for the preparation of electron-transparent TEM specimens. 

We have developed a new method for TEM lamella lift-out using a nanomanipulator with a rotational tip and special holder geometry. This method allows lamella attachment and polishing from the back. After attachment, the lamella is ready for final polishing and in-situ HADF R-STEM imaging without breaking vacuum.

Artefact-free lamella preparation by FIB is crucial for successful TEM analysis. One of the difficulties one faces during the preparation of such specimens is the appearing of curtaining; surface artefacts that arise when polishing a sample which consists of different materials, each with different milling rates.

Failure analysis of microelectronic devices requires routine TEM sample preparation. The lamellae must be site-specific with thicknesses compatible with the technology node. Here we demonstrate lamella preparation from the SRAM array of a commercial processor based on 14 nm technology node. The transistors in such chip are 3D devices known as FinFETs.

Advanced packaging technologies have been developed as a solution to pursue higher functionality, higher density and lower power consumption. Failure analysis of integrated circuit packaging usually requires preparing large area cross-sections. The new TESCAN S8000G FIB-SEM is equipped with the novel Orage™ Ga FIB column capable of a maximum ion beam current of 100 nA which makes it possible to prepare large-area cross-sectioning of solder balls in an automatic and precise way. This increases throughput in the workflow of failure analysis in packaging technologies.

The possibility of consistent and efficient inspection throughout the entire manufacturing process of semiconductor devices is one of the key attributes for high yields and profitability. Feedback on control of each manufacturing step is absolutely necessary, especially during the mass production of wafers (tens of millions of devices per week). Checking layer thicknesses, step coverage, geometry of critical details, depth of trenches, etc. is carried out in order to find defects, their origin and implement appropriate corrective measures.

Visual inspection is an integral part of the production line in all semiconductor foundries. Most of the inspection techniques currently in use are optical-based which will face a resolution limit due to the continual reduction in the size of dies. TESCAN’s Image Snapper is a perfect substitution allowing nondestructive imaging based on the stitching of high magnification images resulting in one high resolution panorama image.

FIB tomography has become an important tool for studying materials at the micro and nano scale. Unlike a single cross-section, FIB tomography gives better understanding of the volume distribution, 3D structure and the relationship between three dimensional objects. TESCAN FIB-SEMs can be equipped with 3D Tomography - an optional software module for automated data acquisition and reconstruction.